Phased caches were previously introduced as cache architecture to reduce the redundant and high-energy consumption caused by reading all data ways on every cache access even though only one of them will be used if the access hits the cache. Phased caches do not query the data arrays in the first cycle of access but rather, wait until a hit is determined before accessing the specific data way hit. This saves dynamic read energy but static energy consumption is not reduced since both the tag and data arrays are ON throughout the program execution.
The rapid increase in microprocessor speed has exceeded the rate of improvement in DRAM (Dynamic Random Access Memory) speed in recent years. This widening performance gap between processors and memories has created several challenges for computer designers since memory performance can easily become a bottleneck to overall system performance. Specifically, processor performance has been observed to increase at about 60% annually, while memory systems lag significantly behind at about 10% annual improvement. To solve this problem, designers turn to memory performance improvements which ultimately dictate the performance and power consumption of processors.
Caching is a common approach used to achieve memory system speed up, by storing data that has been recently used in faster memory. Therefore, using a larger cache could increase the access hit rate, which in turn improves processor speed but this comes at a cost—increased hardware and higher static and dynamic energy consumption.
As a result, there is usually a trade-off between energy and performance in memory system design, since not all accessed memory locations can be stored in faster memories such as caches. Current memory systems designed with SRAMs, DRAMs and/or CAMs, have not been able to catch up with processor performance. As a result, larger caches are often employed in memory systems to bridge this memory processor performance gap. While these large caches offer improved performance, they also increase the power consumed by the processor. An alternative to improve performance is associativity, but it also leads to increased power consumption due to parallel querying of multiple tags. This increasing cache power consumption resulting from the drive for improved performance, cannot be overlooked because caches contribute a significant fraction of the overall power consumed by modern processors. Several authors have concluded that cache/memory systems contribute 30-60% of the total power consumed by processors.
Reducing cache size in an attempt to save power is not an option either, because it leads to higher miss rates and effectively more energy consumption. As a result, several attempts have been made to reduce voltages and design lower power circuits to reduce the high proportion of power consumed by caches/memory systems. However, these circuit level techniques have not been very successful; rather, power dissipation levels have steadily increased with each new microprocessor generation, leading to a renewed interest in architectural approaches that reduce the switching capacitive power component of memory systems without sacrificing performance. In an attempt to save power, some researchers have directed their architectural improvements at better performance because of the observation that improved performance (i.e. less misses) usually lead to less power consumption. Others focus on power reduction techniques targeted at specific aspects of the architecture, with some trade off in performance.